`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:32:28 04/05/2011 
// Design Name: 
// Module Name:    IDtoEX_Buffer 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module IDtoEX_Buffer(clk, pcIn, RegWriteIn, MemtoRegIn, BranchIn, MemReadIn, MemWriteIn, 
	ALUSrc1In, ALUSrc2In, ALUOpIn, readData1In, readData2In, signExtendIn, RsIn, RtIn, writeDstIn, mtIn,
	pcOut, RegWriteOut, MemtoRegOut, BranchOut, MemReadOut, MemWriteOut, ALUSrc1Out, 
	ALUSrc2Out, ALUOpOut, readData1Out, readData2Out, signExtendOut, RsOut, RtOut, writeDstOut, mtOut);
	
	input clk;
	input [15:0] pcIn;
	input RegWriteIn, MemtoRegIn, BranchIn, MemReadIn, MemWriteIn, ALUSrc1In, ALUSrc2In;
	input [3:0] ALUOpIn;
	input [15:0] readData1In, readData2In, signExtendIn, mtIn;
	input [3:0] writeDstIn;
	//added for forwarding
	input [3:0] RsIn;
	input [3:0] RtIn;
	
	output [15:0] pcOut;
	output [15:0] readData1Out, readData2Out, signExtendOut, mtOut;
	output [3:0] writeDstOut;
	output RegWriteOut, MemtoRegOut, BranchOut, MemReadOut, MemWriteOut, ALUSrc1Out, ALUSrc2Out;
	output [3:0] ALUOpOut;
	//added for forwarding
	output [3:0] RsOut;
	output [3:0] RtOut;
	
	reg [15:0] pcOut;
	reg [15:0] readData1Out, readData2Out, signExtendOut, mtOut;
	reg [3:0] writeDstOut;
	reg RegWriteOut, MemtoRegOut, BranchOut, MemReadOut, MemWriteOut, ALUSrc1Out, ALUSrc2Out;
	reg [3:0] ALUOpOut;	
	reg [3:0] RsOut;
	reg [3:0] RtOut;
	
	//access it during the positive edge
	always@(posedge clk)
	begin
		pcOut <= pcIn;
		RegWriteOut <= RegWriteIn;
		MemtoRegOut <= MemtoRegIn;
		BranchOut <= BranchIn;
		MemReadOut <= MemReadIn;
		MemWriteOut <= MemWriteIn;
		ALUSrc1Out <= ALUSrc1In;
		ALUSrc2Out <= ALUSrc2In;
		ALUOpOut <= ALUOpIn;
		readData1Out <= readData1In;
		readData2Out <= readData2In;
		signExtendOut <= signExtendIn;
		writeDstOut <= writeDstIn;
		mtOut <= mtIn;
		RsOut <= RsIn;
		RtOut <= RtIn;
	end

endmodule
